As feature sizes of VLSI circuits continue to shrink,manufacturing process variation and device ageing are resulting in increasing delay variability and lower reliability.The assumption that all chips are identical will result in the need of employing large design margins to accommodate worst-case delays.This significantly erodes the gains obtained through technology scaling.Configurable technology such as Field Programmable Gate Arrays offers a new approach to future digital VLSI designs,which may alleviate this problem.By incorporating on-chip delay measurement techniques to characterize devices individually,each device can be configured to suit its own characteristics for a given design.This approach yields many potential benefits: better timing yield,lower operating voltage and reduced energy consumption,increased life expectancy and improved reliability.In this talk,the potential of combining on-chip measurement techniques with the power of reconfigurability will be exposed and demonstrated.