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5. A Dual-Edge Sampling CES Delay-Locked Loop Based Clock and Data Recovery Circuits

A Dual-Edge Sampling CES Delay-Locked Loop Based Clock and Data Recovery Circuits

来源 :2015 International Symposium on VLSI Design, Automation and | 被引量 : 0次 | 上传用户：net130130

【摘 要】

：

This paper presents a dual-edge sampling clock-embedded signaling CES DLL based CDR.By combining the proposed dual edge sampling and half-UI embedded clock codi

【作 者】

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Jih-Ren Goh Yen-Long Lee Soon-Jyh Chang 

【机 构】

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NationalChengKungUniversity,Taiwan

【出 处】

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2015 International Symposium on VLSI Design, Automation and

【发表日期】

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2015年4期

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论文部分内容阅读

This paper presents a dual-edge sampling clock-embedded signaling CES DLL based CDR.By combining the proposed dual edge sampling and half-UI embedded clock coding,the proposed method can save 4 times number of the required delay cells compared to the conventional DLL,enhancing the power efficiency and reducing silicon area.

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