PMIC (power management integrated chip) devices become more and more important when more and more different chips integrated together. Such as in cell phone devices and other personal portable devices,it provides and manages the power of different cores including digital core, mixed-signal core, external interface core and RF core and the external battery. In a generic PMIC device, there are lots of LDOs (low drop out linear regulator). The load regulation test of LDO is most important and need large current load ranges from 50mA to 500mA which brings challenges to test stability. In production test of load regulation,the test results are very sensitive to the resistance of the path. The contact resistors causes big correlation issues which highly impact the yield of wafers or chips. In design phase of PMIC devices, designers should consider it and design some extra circuits for testing. But DFT (design for test) also brings some problems such as extra pads or increase the size of devices. The design engineers need balance the chip cost and production stability. How to do it? This paper firstly introduces PMIC devices and LDO load regulation test then points out two DFT ways to solve the contact resistors issue. It also covers the advantages and disadvantages of these two DFT solutions. At the end the paper provides an ATE solution on 93000 with Verigys DC scale instruments.