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本文描述了在我们开发的二维版图压缩器中使用的约束图模型,它按照版图中各掩模层和派生层在电学特性或设计规则上的互相影响,把版图划分成若干个逻辑平面。先由各逻辑平面生成相应的约束图,再根据各逻辑平面生成的子约束图形成整个版图的约束图。并利用改进的垂直平面扫描算法生成由约束图模型定义的约束图。
This paper describes the constrained graph model used in the 2D layout compressor we developed. It divides the layout into several logical planes according to the mutual influence of the mask layers and derived layers in the layout on the electrical characteristics or design rules. First, each logical plane generates a corresponding constraint graph, and then generates a constrained graph of the entire topology according to the sub-constraint graphs generated by each logical plane. And use the improved vertical plane scan algorithm to generate the constraint map defined by the constraint graph model.