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H.264编码器中的帧内4×4预测部分具有严重的数据依赖性,它的硬件化设计很难采用流水线实现,从而导致关键路径很长,硬件利用率很低,成为H.264编码器设计中的一个瓶颈。针对这个问题,在不减少预测模式和不增加系统资源的前提下,提出了一种新的结构,它通过利用原始像素进行模式判决和利用重构像素进行帧内预测的方法,可以使帧内预测与重构循环完全流水线实现,基本上达到了100%的硬件利用率,而且没有明显的PSNR损失。所提出的硬件结构可在215个时钟周期内完成一个宏块的帧内4×4预测。用SMIC 0.13μm工艺库综合,结果显示该结构最高可运行在250 MHz,面积约为116千门,可支持4 096×2 160@30 f/s(帧/秒)视频序列的实时编码。
The 4 × 4 prediction part in H.264 encoder has serious data dependency. Its hardware design is hard to adopt in pipelining, resulting in a long critical path and a low hardware utilization ratio, making it an H.264 encoding A bottleneck in device design. Aiming at this problem, a new structure is proposed without reducing the prediction mode and without increasing the system resources. By using the original pixel for pattern decision and the intra prediction using reconstructed pixels, the intra Predictive and reconstruction cycles are fully pipelined and basically achieve 100% hardware utilization without significant loss of PSNR. The proposed hardware architecture achieves an intra 4 × 4 prediction of one macroblock in 215 clock cycles. Synthesized with the SMIC 0.13μm technology library, the results show that the structure can run at up to 250 MHz with an area of approximately 116,000 and can support real-time encoding of 4 096 × 2 160 @ 30 f / s video sequences.