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文中针对运动估计芯片中极为重要的存储器的结构设计，提出了一种降低局存与运算阵列端口数的设计方法，使局存的控制结构得到极大简化．文中应用这种方法，对ＡＢ２，ＡＳ２结构进行改造，得到两种具有工程实用性的新型结构．端口数的降低会带来运算阵列计算效率的下降，为此又推导了一个平衡端口数与计算效率的公式．本文研究来自于实现运动估计芯片的工作中，对研究ＭＰＥＧ－２视频编码器的ＶＬＳＩ实时实现有一定的参考价值．
In this paper, aiming at the structure design of the most important memory in the motion estimation chip, a design method to reduce the number of ports in the array and operation array is proposed, which greatly simplifies the existing control structure. In this paper, we use this method to rebuild the structure of AB2 and AS2, and get two new structures with engineering practicability. The reduction of the number of ports will lead to the decrease of computation efficiency of the arithmetic array. To this end, a formula for balancing the number of ports and calculating efficiency is derived. In this paper, the research comes from the realization of motion estimation chip work, to study the MPEG-2 video encoder VLSI real-time implementation has some reference value.