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提出一种带有列共用结构的电容跨阻放大器(CTIA)读出结构,以实现高线性度、低功耗、低噪声和较大输出范围。该结构可以降低像素结构的复杂性,提高电路设计的灵活度。电路采用奇偶行交替连续读出的方式。采用0.35μm DPTM工艺,利用该结构设计一个原型芯片。电源电压为5 V,每列CTIA结构功耗约为29.3μW,线性度为99.98%。该原型芯片可以被扩展为320×240阵列。
A capacitance-based transimpedance amplifier (CTIA) readout architecture with column common structure is proposed to achieve high linearity, low power consumption, low noise and large output range. The structure can reduce the complexity of the pixel structure and improve the flexibility of the circuit design. The circuit adopts the way that the parity line alternates and reads continuously. Using a 0.35μm DPTM process, a prototype chip is designed using this structure. The power supply voltage is 5 V, the power consumption of each column of CTIA structure is about 29.3μW, the linearity is 99.98%. The prototype chip can be expanded to 320 × 240 array.