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采用高压18V CMOS集成电路工艺,设计了一种开关电容闭环加速度计接口电路芯片。芯片电路中包括开关电容型电荷敏感放大器,PID控制电路以及相关双采样电路。采用相关双采样技术并用大面积PMOS晶体管作前级放大器输入级来消除放大器的1/f噪声、失调电压及KT/C噪声;用高环路增益及静电力平衡技术消除后级电路的1/f噪声、电荷注入和时钟馈通。在相同电极的条件下,利用电荷检测与静电力反馈时域分离法,有效地消除了驱动馈通的影响。设计的芯片采用18V电源电压供电,闭环加速度计刻度因子为420mV/g,噪声密度为10μg/2～1/(Hz) ,芯片面积为15.2mm2。
Using high-voltage 18V CMOS integrated circuit technology, a switched-capacitor closed-loop accelerometer interface circuit chip was designed. The chip circuit includes a switched capacitor charge-sensitive amplifier, a PID control circuit, and associated double sampling circuits. Eliminate the 1 / f noise, offset voltage and KT / C noise of the amplifier by using the correlated double sampling technique and using a large area PMOS transistor as the preamplifier input stage. Eliminate the 1 / f noise of the post-stage circuit by high loop gain and electrostatic force balance, f noise, charge injection and clock feedthrough. In the same electrode conditions, the use of charge detection and electrostatic force feedback time-domain separation method, effectively eliminating the impact of feedthrough. The designed chip is powered by an 18V supply voltage. The scale factor of the closed-loop accelerometer is 420mV / g, the noise density is 10μg / 2 ~ 1 / Hz and the chip area is 15.2mm2.