A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines(WLs) and 4096 bitlines(BLs).Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply. A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishment an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines WLs) and 4096 bitlines (BLs) .Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.