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在无线通信系统中,随着集成电路特征尺寸的不断缩小,芯片漏功耗急剧增大,漏功耗减小技术已成为低功耗无线通信系统设计技术的焦点之一。针对基于功控技术的触发器在休眠状态数据丢失问题,该文提出了一种新型低漏功耗数据保持触发器方案。该触发器使用高阈值的NMOS管作为功控开关以减小触发器休眠期间的漏功耗,使用辅助反相器结合从锁存器中的反相器构成数据存储单元,具有简洁的操作时序。用HSPICE对所设计的触发器进行仿真,结果显示所设计的触发器具有正确的逻辑功能,与传统数据保持触发器相比具有更为简单的操作时序,较低的动态功耗,且休眠漏功耗比传统Mutoh-DFF和DRC-DFF触发器减小了5.6%和24.7%。
In the wireless communication system, as the feature size of the integrated circuit shrinks, the chip drain power consumption increases sharply, and the leakage power reduction technology has become one of the focuses of low power consumption wireless communication system design technologies. Aimed at the data loss of hibernate flip-flop based on power-control technology, a novel data-holding flip-flop with low leakage power is proposed. This flip-flop uses a high-threshold NMOS transistor as a power-controlled switch to reduce the drain power dissipation during the flip-flop hibernation. The use of an auxiliary inverter in combination with the inverter in the latch forms the data memory cell with a simple operation timing . Using HSPICE to simulate the designed flip-flop, the result shows that the designed flip-flop has the correct logic function. Compared with the traditional data-hold flip-flop, the designed flip-flop has simpler operation timing, lower dynamic power consumption, Power consumption is 5.6% and 24.7% lower than traditional Mutoh-DFF and DRC-DFF flip-flops.