针对ASIC芯片物理设计中传统时钟树综合在高频下难以满足时序收敛的问题,提出了一种自下而上与有用时钟偏移相结合的时钟树综合方法。基于TSMC 0.152μm Logic 1P5M工艺,使用Synopsys公司的IC Compiler物理设计软件,采用所提出的方法,完成了一款电力网载波通信芯片的物理设计。结果表明,该方法能够有效构建时钟树,满足建立时间为0.8ns,保持时间为0.3ns的要求,有效保证了PLC芯片的时序收敛。 Aiming at the problem of traditional clock tree synthesis in ASIC chip design that it is difficult to meet timing closure at high frequencies, a clock tree synthesis method combining bottom-up with useful clock offset is proposed. Based on the TSMC 0.152μm Logic 1P5M process and the physical design software of IC Compiler from Synopsys, the physical design of a power line carrier communication chip is completed by the proposed method. The results show that this method can effectively build the clock tree, meet the requirements of 0.8 ns settling time and 0.3 ns hold time, effectively ensuring the timing closure of the PLC chip.