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本文结合用于CMOS图像传感器中的低噪声DPGA的性能特点,提出了一种优化电容阵列拓扑结构的方法,讨论了此种结构下由寄生电容引入的时钟馈通和电荷分配效应,并给出了仿真结果和按照0.35μmCMOS工艺进行流片的版图。测试结果表明,采用改进的电容阵列结构能把采样电容引入的噪声斜率从原来的0.15降低到0.01。
In this paper, we propose a method to optimize the topology of capacitive array based on the performance characteristics of low-noise DPGA used in CMOS image sensor. The effects of clock feed-through and charge distribution introduced by parasitic capacitance are discussed. The simulation results and in accordance with 0.35μmCMOS process flow sheet layout. The test results show that using the improved capacitor array structure can reduce the slope of the noise introduced by the sampling capacitor from 0.15 to 0.01.