论文部分内容阅读
A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 μm standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [?50~100℃] at a 1.8 V supply, and also achieves line regulation of 0.01%/V and ?120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.
A novel high-order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak The proposed circuit, designed with a 0.6 μm standard CMOS technology, gives a good temperature coefficient of 31 ppm / ° C [? 50 to 100 ° C] at a 1.8 V supply, and also achieves line regulation of 0.01% / V and? 120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.