In high-level synthesis of VLSI circuits, good lower bound prediction canefficiently narrow down the large space of possible designs. Previous approaches predict thelower bound by relaxing or even ignoring the precedence constraints of the data flow graph(DFG), and result in inaccuracy of the lower bound. The loop folding and conditional branchwere also not considered. In this paper, a new stepwise refinement algorithm is proposed,which takes consideration of precedence constraints of the DFG to estimate the lower boundof hardware resources under time constraints. Processing techniques to handle multi-cycle,chaining, pipelining, as well as loop folding and mutual exclusion among conditional branchesare also incorporated in the algorithm. Experimental results show that the algorithm canproduce a very tight and close to optimal lower bound in reasonable computation time.