论文部分内容阅读
针对毫米波频段下硅基CMOS晶体管的栅漏寄生电容严重影响放大器的增益和隔离度的问题,采用交叉耦合中和电容抵消其影响,设计了一款60GHz三级差分共源极低噪声放大器(LNA)。为减小级间匹配无源器件的损耗,节省芯片面积,采用变压器进行级间耦合。基于SMIC55nm RF CMOS工艺,进行了电路原理图和版图的设计与仿真。仿真结果显示,该LNA输入输出匹配良好,功率增益为21.1dB,3dB带宽为57.3~61.5GHz,噪声系数为5.5dB,输出1dB压缩点为-0.64dBm,功耗为34.4mW,芯片尺寸为390μm×670μm。
The gate-drain parasitic capacitance of silicon-based CMOS transistors in the millimeter-wave band has a serious impact on the gain and isolation of the amplifier. A 60 GHz three-level differential common-source low-noise amplifier LNA). In order to reduce the loss of interstage matched passive devices and save chip area, transformers are used for the interstage coupling. Based on SMIC55nm RF CMOS process, the circuit schematic and layout design and simulation. The simulation results show that the LNA has a good match between input and output. The power gain is 21.1dB, the 3dB bandwidth is 57.3 ~ 61.5GHz, the noise figure is 5.5dB, the output 1dB compression point is -0.64dBm, the power dissipation is 34.4mW and the chip size is 390μm × 670 μm.