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针对埋栅型静电感应晶体管 (SIT)提出一种柱栅模型 .用镜像法计算了器件内电势分布 ,并在此基础上计算了沟道势垒、栅效率、电压放大因子等 .结果表明 :沟道势垒直接取决于沟道过夹断因子 ;栅效率随栅尺寸和位移栅压的减小而减小 ,并随位移栅压一起趋向于 0 ;在小电流情况下电压放大因子随电流的增大而增大 ,到一定数值后 ,电压放大因子趋于常数 .最后给出了SITI V特性解析表达式 ,它既适用于类三极管特性 (加大栅压下 )也适用于混合特性 (较小栅压下 ) ,且由此得到的I V特性曲线和实验符合较好 .
A kind of pillar grid model is proposed for buried gate electrostatic induction transistor (SIT). The potential distribution in the device is calculated by the mirror method, and the channel barrier, gate efficiency and voltage amplification factor are calculated. The results show that the ditch The channel barrier depends directly on the channel pinch-off factor. The gate efficiency decreases as the gate size and displacement gate voltage decrease, and tends to 0 with the gate shift voltage. In the case of small current, the voltage amplification factor varies with the current Increases and then increases to a certain value, the voltage amplification factor tends to be constant.At last, an analytical expression of SITI V characteristic is given, which is not only suitable for the triode characteristics (under the gate voltage increase) but also for the mixing characteristics Small gate depression), and the resulting IV characteristic curve and the experiment is better.