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设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。
A sample and hold circuit is designed that reduces the power consumption of a 12-bit 40 MHz sample-rate pipelined ADC. Through the time division multiplexing of the op amp, a circuit module not only realizes the sample and hold function, but also realizes the MDAC function and achieves the purpose of reducing the power consumption of the entire ADC. By improving the traditional gate voltage bootstrap switch, reducing the nonlinear distortion of the circuit. By optimizing the bandwidth of the auxiliary op amp, high-gain op amps are fast and stable. The design is implemented in the TSMC 0.35μm mix signal 3.3 V process with a 85-MHz dynamic range (SFDR) and a signal-to-noise ratio (SNDR) of 72 dB at a 40-MHz sampling frequency with an input signal of Nyquist, The effective number of bits (ENOB) is 11.6 bit, and the entire circuit consumes 14 mW of dynamic power.