论文部分内容阅读
目前,在基于FPGA的滤波器设计中,仍然不能同时很好地减小面积消耗和传输延时。分布式算法(DA)由于具有节省硬件资源的优势而被广泛应用于FIR滤波器设计,但在某些系统的设计中,资源消耗和传输延迟仍然不能满足要求。针对分布式算法存在的问题,设计了一种基于LUT的改进FIR滤波器,在相同的滤波要求下,面积消耗和传输延迟更低。在QUARTUS II上分别对DA算法实现的滤波器及改进LUT结构实现的滤波器进行综合仿真,结果表明,改进LUT结构实现的滤波器节省近15%的面积,而且具有更低的延时。
At present, in the FPGA-based filter design, the area consumption and the transmission delay can not be reduced well at the same time. Distributed algorithms (DA) are widely used in FIR filter design because of their advantages of saving hardware resources. However, in some systems, resource consumption and transmission delay still can not meet the requirements. Aiming at the existing problems of distributed algorithm, an improved LUT-based FIR filter is designed. With the same filtering requirements, the area consumption and transmission delay are lower. A comprehensive simulation of the filters implemented by the DA algorithm and the filters implemented with the improved LUT structure is carried out on the QUARTUS II. The results show that the filter with the improved LUT structure can save nearly 15% of the area and has a lower delay.