An innovative, thermally-insensitive phenomenon of cascaded cross-coupled structures is found. And a novel CMOS temperature sensor based on a cross-coupled structure is proposed. This sensor consists of two differ- ent ring oscillators. The first ring oscillator generates pulses that have a period, changing linearly with temperature. Instead of using the system clock like in traditional sensors, the second oscillator utilizes a cascaded cross-coupled structure to generate temperature independent pulses to capture the result from the first oscillator. Due to the compen- sation between the two ring oscillators, errors caused by supply voltage variations and systematic process variations are reduced. The layout design of the sensor is based on the TSMC13G process standard cell library. Only three inverters are modified for proper channel width tuning without any other custom design. This allows for an easy integration of the sensor into cell-based chips. Post-layout simulations results show that an error lower than ±1.1 °C can be achieved in the full temperature range from 40 to 120 °C. As shown by SPICE simulations, the thermal insensitivity of the cross-coupled inverters can be realized for various TSMC technologies: 0.25 μm, 0.18 μm, 0.13 μm, and 65 nm. An innovative, thermally-insensitive phenomenon of cascaded cross-coupled structures is found. And a novel CMOS temperature sensor based on a cross-coupled structure is proposed. This sensor consists of two differ- ent ring oscillators. The first ring oscillator generates pulses that Instead of using the system clock like in traditional sensors, the second oscillator utilizes a cascaded cross-coupled structure to generate temperature independent pulses to capture the result from the first oscillator. Due to the compen- sation between the two ring oscillators, errors caused by supply voltage variations and systematic process variations are reduced. The layout design of the sensor is based on the TSMC 13G process standard cell library. Only three inverters are modified for proper channel width tuning without any other custom design . This allows for easy integration of the sensor into cell-based chips. Post-layout simulations results sh ow that an error lower than ± 1.1 ° C can be achieved in the full temperature range from 40 to 120 ° C. As shown by SPICE simulations, the thermal insensitivity of the cross-coupled inverters can be realized for various TSMC technologies: 0.25 μm , 0.18 μm, 0.13 μm, and 65 nm.