数字锁相环是闭环自动控制系统,常用于接受信号的载波恢复与跟踪。文章介绍了一种二阶数字锁相环的基本原理和其基于FPGA的实现方案,详细阐述了鉴相器、环路滤波器和数控振荡器等环路部件的参数设计及电路结构,并引入一种有效的环路状态检测方法,仿真验证了设计的正确性和有效性。 Digital PLL is a closed-loop automatic control system, commonly used to receive signal carrier recovery and tracking. In this paper, the basic principle of a second-order digital phase-locked loop and its implementation scheme based on FPGA are introduced. The parameter design and circuit structure of loop components such as phase detector, loop filter and numerically controlled oscillator are described in detail. An effective method of loop state detection, the simulation verifies the correctness and effectiveness of the design.