【摘 要】
：
The test vector compression is a keytechnique to reduce IC test time and cost since theexplosion of the test data of system on chip (SoC) inrecent years. To reduce the bandwidth requirementbetween the
【出 处】
：
Journal of Electronic Science and Technology of China
论文部分内容阅读
The test vector compression is a keytechnique to reduce IC test time and cost since theexplosion of the test data of system on chip (SoC) inrecent years. To reduce the bandwidth requirementbetween the automatic test equipment (ATE) and theCUT (circuit
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