现代晶闸管阀的高额定容量使其难以在试验室用背靠背试验回路进行试验,用合成试验回路对晶闸管阀的设计进行验证是一种替代方法。设计合成试验回路的核心在于,如何正确地再现作用在晶闸管阀上的负荷。为此,重点描述了换流阀在4种运行状态下的电压和电流负荷。ABBPowerSystems开发了一种新的合成试验回路,正确地再现了运行中施加在HVDC晶闸管阀上的电压和电流负荷。验证试验表明,该回路的设计是成功的。 The high rated capacity of modern thyristor valves makes it difficult to test back-to-back test circuits in the laboratory and the design of thyristor valves using synthetic test circuits is an alternative. The heart of the design synthesis test loop is how to correctly reproduce the load acting on the thyristor valve. To this end, the emphasis is placed on the voltage and current load of the converter valve in four operating states. ABBPowerSystems has developed a new synthesis test loop that correctly reproduces the voltage and current loads that are applied to HVDC thyristor valves during operation. Verification tests show that the design of the circuit is successful.