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本文提出一种沟道长度为0.125μm的异质结CMOS(HCMOS)器件结构。在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析。模拟结果表明,相对于体SiCMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成。
This paper presents a heterojunction CMOS (HCMOS) device structure with a channel length of 0.125 μm. In this structure, compressively strained SiGe and tensile strained Si are respectively used as the channel materials for the heterojunction PMOS (HPMOS) and the heterojunction NMOS (HNMOS), and the HPMOS and the HNMOS are vertically stacked structures; in order to accurately simulate the The electrical properties of the devices were modified to correct the hole and electron mobility models of strained SiGe and strained Si. The DC and AC characteristics of the device and the input and output characteristics were simulated and analyzed using Medici software. The simulation results show that the device has better electrical characteristics, the correct logic function and shorter delay time compared to the bulk SiCMOS devices, and the vertical stack structure can also save about 50% of the layout Area, is conducive to the further integration of the circuit.