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提出了一种嵌入式标准化I2C从机设计方案,对传统I2 C从机的状态机进行简化,得到了改进型状态机。综合结果表明,与传统状态机相比,改进型状态机的面积减少约20%,功耗降低约4%。以一款芯片为例,详细介绍了I2 C总线嵌入式开发过程。该方案已通过功能仿真、FPGA验证及版图后仿真。对该电路进行FPGA验证,构建了一种简单、高效的FPGA验证系统。
An embedded standard I2C slave design scheme is proposed, which simplifies the state machine of traditional I2C slave and obtains an improved state machine. The results show that compared with the traditional state machine, the area of the improved state machine is reduced by about 20% and the power consumption is reduced by about 4%. Take a chip as an example, introduced the embedded development process of I2 C bus in detail. The program has passed the functional simulation, FPGA verification and layout simulation. FPGA verification of the circuit to build a simple and efficient FPGA verification system.