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传统的可重构电路主要由细粒度数据处理单元组成,但是其实现的运算功能单一,且布线复杂,限制了可重构SoC电路的通用性和灵活性。针对以上问题,根据通信领域基带信号处理的运算特点,设计了一种新型可重构阵列电路,可作为运算模块嵌入可重构SoC,此阵列由粗粒度数据处理单元构成的细胞互联组成。针对基带信号数据位宽多样的特点,细胞可重构实现多种算子。通过在阵列中每个细胞内部都嵌入独立配置存储器,采用并行数据配置电路的方式,以降低阵列的重构时间开销,实现整个阵列的快速重构。以伪码捕获为例,对设计的电路进行仿真。结果显示,设计的结构布线方法简单、通用性及灵活性强。
Traditional reconfigurable circuits are mainly composed of fine-grained data processing units. However, their single-function operation and complicated routing limit the versatility and flexibility of reconfigurable SoC circuits. In view of the above problems, a new type of reconfigurable array circuit is designed according to the operation characteristics of baseband signal processing in communication field. It can be used as an arithmetic module to embed a reconfigurable SoC. The array consists of cellular interconnects formed by coarse-grained data processing units. For the wide range of baseband signal data characteristics, the cell can be reconfigured to achieve a variety of operators. By embedding the independent configuration memory inside each cell in the array and configuring the circuit with parallel data, the reconfiguration time overhead of the array is reduced, and the entire array is quickly reconfigured. Taking pseudo-code capture as an example, we simulate the designed circuit. The results show that the design of structured cabling method is simple, versatile and flexible.