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对主从型 D触发器的功能及时序进行分析 ,证明了该类型触发器无效功耗的存在 ;文章建立了无效功耗的数学模型 ,并通过对典型应用电路的理论推导和计算机模拟 ,验证了这一结论的正确性。分析无效功耗的目的是为了采取措施消除其影响 ,文中提出的数学模型对低功耗 VL SI设计有着重要的价值。
This paper analyzes the function and timing of master-slave D flip-flop and proves the existence of invalid power dissipation of the flip-flop of this type. The article establishes the mathematical model of invalid power consumption, and through the theoretical derivation and computer simulation of typical application circuit, The correctness of this conclusion. The purpose of analyzing the ineffective power consumption is to take measures to eliminate its influence. The mathematical model proposed in this paper is of great value for low power VLSI design.