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为了满足产品上市时间和功能丰富性的要求,越来越多的先进设计公司开始提高设计的抽象层次进行复杂的DSP硬件设计,从RTL级提高到C/C++,以保持产品的持续领先地位。Mentor Graphics的高层次综合工具(Catapult Synthesis)是第一个综合标准的ANSI C++的产品,它可无误地生成针对ASIC/FPGA的高质量RTL代码,且速度比手工编码的快10-20倍。本文以FIR的实现为例,利用Catapult Synthesis快速探索不同的设计架构,快速地找到性能、面积和功耗之间折衷的最佳实现方案,使得真正的IP复用成为可能,并以图表方式给出不同约束下的面积、延迟和吞吐率(36、3、1时钟周期)的性能,同时提供了集成的验证和综合流程,极大地提高了设计效率。
In order to meet the time-to-market and feature-rich requirements, more and more advanced design companies are beginning to raise the design abstraction level for complex DSP hardware design, from RTL level to C / C ++, in order to maintain the product’s continued leading position. Mentor Graphics’ Catapult Synthesis is the first comprehensive standard ANSI C ++ product that produces high-quality RTL code for ASICs / FPGAs without errors, at 10-20 times faster than manual coding. In this paper, FIR implementation, for example, the use of Catapult Synthesis to quickly explore different design architecture, and quickly find the best compromise between performance, area and power consumption of the program, making the real IP multiplexing possible and graphically The performance under different constraints of area, latency, and throughput (36, 3, 1 clock cycles) while providing an integrated verification and synthesis flow dramatically improves design efficiency.