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在数字逻辑系统中,延迟线有许多重要的作用.本文介绍一个可编程、多通道的延迟系统,其特点是简单、价格低、采用的元件少.虽然电路不复杂,但可在字宽和字长方面进行扩充;在工作过程中,其延迟时间可在0.1微秒至10秒之间变动,而且还可以由微处理机(或随机—逻辑电路)控制.为了实现延迟,电路采用了一个FIFO(先进先出)缓冲器作为一个字宽移位寄存器.可编程宽度为N(见图1).8位字输入中的每一位可以看作是一个单独的通道,所有的通道同时被延迟.写入到FIFO 中的数目,在FIFO 里一直是保持固定的.于是,每个字在输出之前必须在FIFO 缓冲器里穿过N 次.这一动作过程就产生了延迟.如果将FIFO缓冲器并联,就可以增加字宽或通道数目;如果将FIFO 缓冲器串联,就可以增加字长或延迟时间.时钟输入速率确定了电路的延迟分辨率.操作的初始阶段包括将N 个任意字装入到FIFO 缓冲器
In the digital logic system, the delay line has many important functions.This article introduces a programmable, multi-channel delay system, which is characterized by simple, low cost, using fewer components.Although the circuit is not complicated, but in the word width and The word length of the expansion; in the course of their work, the delay time can be changed between 0.1 microseconds to 10 seconds, but also by the microprocessor (or random - logic) control.In order to achieve the delay, the circuit uses a The FIFO (first-in, first-out) buffer acts as a word-width shift register with a programmable width of N. Each of the 8-bit word inputs can be thought of as a separate channel with all channels being simultaneously Delay. The number of writes to the FIFO is always fixed in the FIFO. Therefore, each word must be passed through the FIFO buffer N times before it is output. This delay causes a delay. If the FIFO Buffers in parallel can be used to increase the word width or the number of channels and word length or delay can be added if the FIFO buffers are in series.The clock input rate determines the delay resolution of the circuit.The initial phase of operation consists of adding N arbitrary words Load into FIF O buffer