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设计了一种基于CMOS工艺的高速采样保持电路。该电路采用了开环双路双差分结构。详细分析了引起电路非线性的原因,并采用了新的结构来提高电路的线性度。仿真结果表明,在电源电压为1.9V,输入信号频率为393.75MHz,采样率为1.6GS/s,负载为0.5pF时,该电路的无杂散动态范围(SFDR)为80.5dB,总谐波失真(THD)为-78.6dB,有效位为12.7位。该电路具有高采样率、高SFDR和较强驱动能力等优点。
A high speed sampling and holding circuit based on CMOS technology is designed. The circuit uses an open loop dual dual differential architecture. The causes of circuit nonlinearity are analyzed in detail, and a new structure is adopted to improve the linearity of the circuit. The simulation results show that the SFDR of the circuit is 80.5dB with the power supply voltage of 1.9V, the input signal frequency of 393.75MHz, the sampling rate of 1.6GS / s and the load of 0.5pF. The total harmonic The distortion (THD) is -78.6dB, the effective bit is 12.7 bits. The circuit has the advantages of high sampling rate, high SFDR and strong drive capability.