论文部分内容阅读
通过对高级加密标准AES算法进行描述,给出了基于FPGA设计的具体设计流程和方法。采用多轮加密过程共用一个轮运算的顺序结构。由于文中的加密模块与解密模块采用相关且不同的初始密钥和不同的密钥扩展模块,结果加强了通信的安全性。采用16位并行总线数据结构,利用16位输入128输出的FIFO数据缓存器对输入数据进行缓存,从而完成数据的加解密。最后通过ISE 13.1仿真验证了该算法设计的正确性。
Through the description of the advanced encryption standard AES algorithm, the specific design flow and method based on FPGA design are given. Use multiple rounds of encryption process share a round of operation of the order structure. As the encryption module and the decryption module in the text adopt different initial keys and different key expansion modules, the result strengthens the communication security. 16-bit parallel data bus architecture, a 16-bit output from the FIFO 128 input data buffer buffers the input data, thereby completing the data encryption and decryption. At last, the correctness of this algorithm is verified by ISE 13.1 simulation.