The authors theoretically describe the monotonic increasing relationship between averagepowers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, whichcan be fast computed, has been used as the evaluation criterion for the power of a practical circuit withdelay, which needs more computing time, in such fields as fast estimation for the average power and themaximum power, and fast optimization for the Iow test power. The authors propose a novel simulationapproach that uses delay-free power to compact a long input vector pair sequence into a short sequenceand then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. Incomparison with the traditional simulation approach that uses an un-compacted input sequence to simu-late the average (or maximum) power, experiment results demonstrate that in the field of fast estimationfor the average power, the present approach can be 6-10 times faster without significant loss in accuracy(less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach canbe 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast op-timization for the test power, the authors propose a novel delay-free power optimization approach for thetest power. Experiment results demonstrate that, in comparison with the approach of direct optimizationand the approach of Hamming distance optimization, this approach is of the highest optimization effi-ciency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% testpower).