论文部分内容阅读
锁相环作为片内高速时钟的提供者,在现代电路中至关重要。提出了一种全数字锁相环的设计方案,输出频率为250 MHz,锁定时间为2μs,峰峰抖动为76ps,与传统锁相环相比,具有面积小、功耗低、可移植性好、抗干扰能力强等优点。时间数字转换器(TDC)是全数字锁相环的重要组成部分,采用线性增强算法后,与现有TDC相比,具有动态范围大、分辨率高等特点,且大大减小了积分非线性。
Phase-locked loop as a high-speed clock chip provider, in modern circuits is crucial. A digital phase-locked loop design is proposed. The output frequency is 250 MHz, the lock time is 2μs and the peak-to-peak jitter is 76ps. Compared with the traditional PLL, it has the advantages of small area, low power consumption and good portability , Anti-interference ability and so on. Time-to-digital converter (TDC) is an important part of all digital phase-locked loop. Compared with the existing TDC, the TDC has the characteristics of large dynamic range and high resolution, and greatly reduces the integral nonlinearity.