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随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路。本文提出,用ROM(Read—Only Memory)做为运算单元的多输入并行加法网络的构成方法。首先,提出能够处理补码的并行计数器ROM。其次,提出用计数器ROM 作为基本组成单元的多输入并行加法网络的构成算法。最后,推导求出多输入并行加法网络所需的ROM 数的公式,并对影响速度的级数进行讨论。本文提出的多输入并行加法网络有对于任何加权(Weight)的输入都可以进行高速处理的特长。因此,这种电路很适合于高速乘一加运算电路和卷积运算电路,以及高速数字滤波器电路。
With the rapid development of integrated circuits, it is possible to use memory components to implement the arithmetic circuit. This paper presents a method of constructing a multi-input parallel addition network using ROM (Read-Only Memory) as an arithmetic unit. First, a parallel counter ROM capable of handling complement is proposed. Secondly, the algorithm of constructing a multi-input parallel addition network with a counter ROM as a basic unit is proposed. Finally, the formula for calculating the number of ROM required to find a multi-input parallel addition network is derived and the number of stages that affect speed is discussed. The proposed multi-input parallel addition network has the advantage of high-speed processing for any weight input. Therefore, this circuit is suitable for high-speed multiplication and addition circuit and convolution operation circuit, as well as high-speed digital filter circuit.