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重点介绍了一种适合ＨＤＴＶ的ＲＳ码编译码器乘法器：对偶基比特并行乘法器的算法和实现方案。根据有限域ＧＦ（ｐｍ）中的有关定义和定理导出了对偶基比特并行乘法器的算法；给出了详细的实现电路并举例说明了其应用；简要介绍了其在ＨＤＴＶ的ＲＳ码编译码器中的应用，并和“查表法”实现的乘法器作了比较。说明了对偶基比特并行乘法器在硬件规模上的优越性。
A RS code codec multiplier suitable for HDTV is introduced emphatically. The algorithm and implementation of dual base bit parallel multiplier are introduced. According to the definition and theorem in the finite field GF (pm), the algorithm of the parallel base bit parallel multiplier is derived. The detailed implementation circuit is given and its application is illustrated. The RS code codec In the application, and with the “look-up table” to achieve a comparison of multipliers. This paper illustrates the superiority of dual-bit parallel multiplier in hardware scale.