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为了提高系统芯片的可靠性和性能价格比,增强其市场竞争力,缩小器件特征尺寸并提高集成度仍是一个主要的途径。当器件特征尺寸进入亚50nm以后,大量来自于传统工作模式、传统材料、传统工艺乃至传统器件物理基础等方面的问题将成为器件特征尺寸进一步缩小的限制性因素。因此我们的973项目从新型材料、半导体器件分析、新型器件结构、关键制备工艺等方面开展了深入的研究。本文主要介绍我们在新型半导体器件结构以及制备工艺方面取得的主要成果,具体包括平面双栅器件、金属栅器件、垂直沟道双栅器件、DSOI器件、SON器件、SOI肖特基晶体管、高K介质器件等。
In order to improve the reliability and cost performance of system-on-chip and enhance its market competitiveness, it is still a major way to reduce the feature size and improve the integration of the device. When the feature size of a device enters the sub-50nm range, a large number of problems from the traditional mode of operation, traditional materials, traditional processes and even the physical basis of traditional devices will become the limiting factors for further reducing the feature size of the device. Therefore, our 973 project has conducted in-depth research on new materials, semiconductor device analysis, new device structures, and key preparation processes. This article mainly introduces our main achievements in new semiconductor device structure and fabrication process, including planar double gate devices, metal gate devices, vertical channel double gate devices, DSOI devices, SON devices, SOI Schottky transistors, high K Media devices and so on.