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SDH中C_4映射的码速调整电路是SDH各映射中工作速度最高的。在用专用集成电路实现时，对集成电路的工艺和功耗都提出了很高的要求。本文提出了采用并行处理实现正码速调整的新方法，有效地解决了采用常规串行码速调整电路时工作频率过高的问题，并且利用FPGA对并行码速调整方法进行了实验研究，得出的测试结果优于国际市场上的一些产品。
The code speed adjusting circuit of C_4 mapping in SDH is the highest working speed in each mapping of SDH. In the use of ASIC implementation, the integrated circuit technology and power have made a very high demand. This paper presents a new method of parallel processing to achieve positive code speed adjustment, which effectively solves the problem of high operating frequency when using conventional serial code speed adjusting circuit. And the experimental research on the parallel code speed adjusting method is carried out by using FPGA Out of the test results better than some products on the international market.