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For direct sequence spread spectrum(DSSS) receivers, the capability of rejecting narrow-band interference can be significantly improved by a process of frequency-domain interference suppression(FDIS).The key issue of this process is how to determine a threshold to eliminate interference in the frequency domain,which has been extensively studied.However,these previous methods are tedious or very complex.A simple and efficient algorithm based on medians is proposed.The elimination threshold is only related to the median by a scale factor,which can be obtained by the numerical analysis.Simulation results show that the algorithm provides excellent narrow-band interference suppression while only slightly degrading the signal-to-noise ratio(SNR).A one-pass algorithm using logarithmic segmentation is further derived to estimate medians with low computational complexity. Finally,the FDIS is implemented in a field programmable gate array(FPGA) of Xilinx.Experiments are carried out by connecting the FDIS FPGA to a DSSS receiver,and the results show that the receiver has an effective countermeasure for a 60 dB interference-to-signal ratio(ISR).
The ability of rejecting narrow-band interference can be significantly improved by a process of frequency-domain interference suppression (FDIS). The key issue of this process is how to determine a threshold to eliminate interference In the frequency domain, which has has been extensively studied. Host, these previous methods are tedious or very complex. A simple and efficient algorithm based on medians is proposed. The elimination threshold is only related to the median by a scale factor, which can be obtained by the numerical analysis. Simulation results show that the algorithm provides excellent narrow-band interference suppression while only slightly degrading the signal-to-noise ratio (SNR). One-pass algorithm using logarithmic segmentation is further derived to estimate medians with low computational complexity. Finally, the FDIS is implemented in a field programmable gate array (FPGA) of Xilinx. Experiments are carried out by connecting the FDIS FPGA to a DSSS receiver, and the results show that the receiver has an effective countermeasure for a 60 dB interference-to-signal ratio (ISR).