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提出了一种用于MEMS的硅基SiC微通道(阵列)及其制备方法,它涉及半导体工艺加工硅晶片和化学气相淀积方法制备SiC。在Si(100)衬底上用半导体工艺刻蚀出凹槽微结构,凹槽之间留出台面,凹槽和台面的几何尺寸(深度、宽度、长度)及其分布方式根据需要而定,此凹槽微结构用作制备SiC微通道的模板;用化学气相淀积方法在模板上制备一厚层SiC材料,此层SiC不仅完全覆盖衬底表面的微结构包括凹槽和台面,还在凹槽顶部形成封闭结构,这样就在衬底上形成了以凹槽为模板的SiC微通道(阵列)。对淀积速率与微通道质量之间的关系进行初步分析,发现单纯地提高淀积速率不利于获得高质量的微通道。
A silicon-based SiC microchannel (array) for MEMS and a method for preparing the same are proposed, which relate to a semiconductor process for processing a silicon wafer and a chemical vapor deposition method for preparing SiC. On the Si (100) substrate, a grooved microstructure is etched using a semiconductor process, leaving the mesa, groove, and mesa geometry (depth, width, length) between the grooves and their distribution as desired, The grooved microstructure is used as a template for preparing SiC microchannels. A thick layer of SiC material is prepared on the template by a chemical vapor deposition method. The SiC layer not only completely covers the surface of the substrate but also has microstructure including grooves and mesas. A closed structure is formed at the top of the groove, so that a groove-shaped SiC microchannel (array) is formed on the substrate. The preliminary analysis of the relationship between the deposition rate and the quality of microchannels shows that simply increasing the deposition rate is not conducive to obtaining high quality microchannels.