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为了研究电路实现形式对密码芯片抗“功耗分析攻击”能力的影响,考察了CMOS门电路的交流馈通对电源电流的影响,输入组合对电路充放电网络的影响以及静态电流的数据相关性。对静态逻辑、N/P型动态逻辑和差分Domi-no逻辑的这3种信息泄漏机制进行了具体分析,并对这4种逻辑的2输入与门和或门进行了仿真。静态电路和普通动态电路不同输入变化对应的电流曲线间的最大差值都大于60μA,而差分Domino电路的所有电流曲线之差小于2μA。结果表明:采用N型Domino逻辑,并使数据输入只在时钟为高时有效,相对于其他逻辑功耗信息泄漏要小。
In order to study the effect of the circuit implementation on the anti-power analysis attack ability of the cryptographic chip, the influence of the AC feedthrough on the gate current of the CMOS gate, the influence of the input combination on the charge-discharge network, and the data dependence of the quiescent current . The three kinds of information leakage mechanism of static logic, N / P dynamic logic and differential Domi-no logic are analyzed in detail, and these four logic 2-input AND gates and OR gates are simulated. The maximum difference between the current curves for different input changes of static and normal dynamic circuits is greater than 60μA, while the difference between all current curves for differential Domino circuits is less than 2μA. The results show that N-type Domino logic is used and that data entry is valid only when the clock is high, as opposed to other logical power leakage information.