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提出了一种具有极低通带宽度的二阶全数字销相环，并采用了一些非线性的改进措施，从而使其具有一个相对较宽的牵出范围，以恢复E1支路信号的时钟。硬件实验证实，它完全可以满足ITU－T对抖动抑制特性的要求。同时由于数字集成电路技术成熟，其集成度远远高于模拟集成电路；因而采用全数字锁相环对系统的集成有明显的益处。
A second-order all-digital pin phase-locked loop with extremely low passband width is proposed and some non-linear improvement measures are adopted so that it has a relatively wide pull-out range to recover the clock of the E1 branch signal . Hardware experiments confirmed that it can fully meet the ITU-T jitter suppression features. At the same time as the digital integrated circuit technology is mature, its integration is much higher than the analog integrated circuits; thus using the all-digital phase-locked loop on the system integration has obvious benefits.