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介绍了一种应用于数字通信系统中的新型位同步电路的设计方案,并通过硬件实现了此方案。该方案有效解决了传统位同步提取方法中的一些问题,如电路实现和技术过于复杂的问题、相位模糊、影响系统性能等。电路设计用同系列数字化芯片硬件实现后电路简单稳定,干扰小,同步精度高,跟踪范围比较宽,输入主频低,最后给出了仿真结果和硬件性能测试数据。
A design scheme of a new type of bit synchronization circuit used in digital communication system is introduced and implemented in hardware. The scheme effectively solves some problems in traditional bit synchronization extraction methods, such as the circuit implementation and technology are too complicated, the phase is fuzzy, and the system performance is affected. Circuit design with the same series of digital chip hardware circuit after the simple and stable, small interference, high synchronization accuracy, tracking a wide range, the input frequency is low, and finally gives the simulation results and hardware performance test data.