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在高频信号传输过程中,为避免阻抗不匹配所带来的信号完整性问题,设计了一种适用于高频信号传输的阻抗匹配自校准电路。利用二分查找法快速检测需要并联的不同权重的电阻,根据比较器的比较结果决定是否并入,以达到预期修调阻值的目的。增加了电感器件,以减小外界高频信号的干扰,同时屏蔽输入级的寄生电容。校准完成后,对校准电路进行断电,以节省整体电路功耗。相比于传统简单的并串联电阻修调架构,该结构适用于高频信号的传输,校准精度高,信号传输性能好。采用TSMC 0.18μm标准CMOS工艺进行设计,电源电压为1.8V。仿真结果表明,可实现的最大修调电阻值为98.43Ω,相比预期的100Ω阻值,偏差仅为1.57%。对增加电感前后的电路整体性能进行对比,增加电感后,有效减小了信号反射能量,保障了信号的完整性传输。
In order to avoid the problem of signal integrity caused by impedance mismatch during the transmission of high frequency signals, an impedance matching self-calibration circuit suitable for high frequency signal transmission is designed. The use of binary search method to quickly detect the need for parallel weights of different resistance, according to the comparator to determine whether to incorporate the results in order to achieve the purpose of adjusting the resistance. Increase the inductance device, in order to reduce the interference of the high frequency signal of the outside world, shield the parasitic capacitance of the input stage at the same time. After the calibration is completed, the calibration circuit is powered off to save overall circuit power consumption. Compared with the traditional simple and series resistor trimming architecture, the structure is suitable for transmitting high-frequency signals with high calibration accuracy and good signal transmission performance. Designed with TSMC 0.18μm standard CMOS process, the supply voltage is 1.8V. Simulation results show that the maximum achievable trimming resistance is 98.43Ω, which is only 1.57% deviation from the expected 100Ω resistance. The overall performance of the circuit before and after the increase of inductance compared to increase the inductance, the effective reduction of the signal reflection energy to ensure the integrity of the signal transmission.