提出了一种低功耗连续时间多比特△-∑调制器架构.该架构充分利用了△-∑结构高分辨率和连续时间结构高速度的特点.将量化器的输出分为最高有效位(MSB)和最低有效位(LSB),LSB被反馈到量化器和DAC的输入,提高了系统的分辨率和线性度,降低了系统的硬件复杂度.除此之外,积分器的输出摆幅也显著减小,大大降低了运算放大器对带宽和增益的要求.使用SAR量化器中的开关电容DAC阵列进行环路延迟补偿,进一步提高了环路滤波器功率效率.通过仿真分析,验证了提出架构的正确性.“,”A low power multibit architecture for a continuous-time (CT) delta-sigma (△-∑) modulator with increased resolution and speed was proposed.The proposed architecture divided the output of quantizer into an MSB and an LSB.The LSB was applied to the quantization noise for noise coupling,and was fedback to digital-to-analog converter for noise shaping.As a result,the resolution and linearity were increased.At the same time,the hardware complexity and the output swing of integrator were reduced,which had relaxed greatly the bandwidth and gain requirements of op-amp design.The power efficiency of loop filter was gained further by performing excessloop-delay compensation (ELDC) with the switched capacitor DAC array in the SAR quantizer.The proposed architecture was analyzed and verified through simulation.