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本研制方案的目的是研究硅双极晶体管技术的基本限制。总的说来是要着重解决在1～10千兆赫频段内的单片功率器件的结构上的技术问题。在本方案中,TRW 公司半导体分部的计划包括三个研究阶段。第一阶段是实现顶面集电极与埋层接触,并使埋区到顶面能以很小的电阻损耗来传输功率。第二阶段是处理在单片的硅衬底的特定区域中横向和竖向的射频绝缘,并保证绝缘区中的顶面接触功率器件结构的散热能力。第三阶段是研究匹配元件与单片射频功率器件所需要的有源元件和无源元件之间“非手工引线”互连的限制。本报告也讨论了第三阶段所要求的集总元件匹配网络的设计和工艺程序。
The purpose of this development program is to study the basic limitations of silicon bipolar transistor technology. In general, the technical problems of the structure of monolithic power devices in the frequency band of 1 to 10 gigahertz should be emphasized. In this scenario, the TRW Semiconductor Division's plan includes three research phases. The first stage is to achieve the top collector contact with the buried layer, and the buried area to the top surface with a small resistance loss to transmit power. The second stage is to handle lateral and vertical RF insulation in a specific area of a monolithic silicon substrate and to ensure that the top surface in the insulation area contacts the power dissipating capability of the power device structure. The third phase is to study the limitations of the “non-manual wire” interconnection between the active and passive components required by the matching element and the monolithic RF power device. This report also discusses the design and process procedures for the lumped-element matching network required in the third stage.