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提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tile-based FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也可以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.
A new reconfigurable pipelined multiplier design embedded in FPGA is proposed, which adopts an improved Ports coding algorithm and can realize 18 × 18 signed multiplication or 17 × 17 unsigned multiplication. A new circuit optimization approach is used to reduce the number of partial products and a new layout of multiplier layouts is proposed to accommodate the constraints imposed by tile-based FPGA chip design. The multiplier can be configured for synchronous or asynchronous mode as well Can be configured into a pipeline mode to meet the high-frequency operation.The design is easy to expand into different input and output bit width.At the same time, a new advanced carry adder circuit to produce the final result.Using the transmission gate Logic to achieve the entire multiplier. Multiplier SMIC 0.13μm CMOS process to achieve, to complete 18 × 18 multiplication operation requires 4.1ns. All 2-stage pipeline, the clock cycle can reach 2.5ns. This is more than commercial The multiplier is 29.1% faster, 17.5% faster than other multipliers, which is 1/32 the area of a traditional multiplier compared to a conventional look-up-based multiplier.