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A 25 Gbit/s clock and data recovery(CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethernet(100 Gb E) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company(TSMC) 65 nm complementary metal-oxide-semiconductor(CMOS) technology. A novel quadrature voltage-controlled-oscillator(QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 312-1 pseudorandom bit sequence(PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 m W(excluding output buffers).
A 25 Gbit / s clock and data recovery (CDR) circuit with 1: 2 demultiplexer for 100 Gbit / s Ethernet (100 Gb E) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company (TSMC) 65 nm complementary metal-oxide -semiconductor (CMOS) technology. A novel quadrature voltage-controlled-oscillator (QVCO) structure adopting two pairs of transconductance cells and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector mechanism four flip- flops array to sample the 25 Gbit / s input data and align the data phase, so the 25 Gbit / s data are retimed and demultiplexed into both paths 12.5 Gbit / s output data. Experimental results show that the recovered clock exhibits a peak-to -peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 312-1 pseudorandom bit sequence (PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW excluding output buffers).