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在设计者进行系统和电路级设计时,时常会将要实现的逻辑功能或操作较为平均地分配到时序中的各个阶段,称之为逻辑平衡设计。该论文引用了逻辑平衡的方法,将其运用在高速数字部件设计中,以常用运算单元如计数器,有限状态机和乘法器的高性能设计方案为例,分析了逻辑平衡在高速集成电路设计中的应用;并分析了逻辑平衡的方法在减小电路面积,提高电路的性价比和降低电路功耗中的作用。
When designing system and circuit level designers, designers often allocate the logic functions or operations to be more evenly distributed to each phase of the timing sequence. This is called a logic balanced design. This paper cites the method of logic balance and applies it to the design of high-speed digital components. Taking the high-performance design of common operation units such as counters, finite state machines and multipliers as an example, the paper analyzes the logic balance in high-speed integrated circuit design The application of the logic balance method is also analyzed in reducing the circuit area, improving the circuit cost performance and reducing the circuit power consumption.