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为了满足在一个通信系统中使用多码率RS(Reed-Solomon)码的需求,提出了一种多码率部分并行结构的RS码译码器.按照功能,该译码器可分为伴随式计算模块,关键方程求解模块以及错误位置和错误值求解模块3个主要组成部分.针对符合CCSDS标准的2种RS码的特点,将运算系数相同的伴随式计算子单元进行复用;在关键方程的求解运算中使用一种新颖的部分并行结构,使得复用部分和非复用部分的运算周期相同,以减少运算等待时间,提高译码效率;在错误位置和错误值求解中采用查表方式完成Forney算法的系数相乘,并复用求逆查表运算和系数相同的钱氏搜索计算子单元,以减少资源的消耗.通过码率选择信号,可以选择RS(255,223)和RS(255,239)2种译码模式.通过Altera公司的FPGA(Field Pro-grammable Gate Array)对该多码率译码器进行了硬件实现,结果显示此译码器仅消耗2981个逻辑单元和9472 bit的存储器资源,大大低于2种单一码率译码器消耗资源的总和.
In order to meet the requirement of using multi-rate RS (Reed-Solomon) codes in a communication system, an RS code decoder with multi-bit rate partial parallel structure is proposed. According to the function, the decoder can be divided into the following formulas Calculation module, key equation solving module and error position and error value solving module.According to the characteristics of two kinds of RS codes conforming to the CCSDS standard, the companion sub-units with the same operation coefficient are multiplexed, and in the key equation The use of a novel part of the parallel computing structure, making the multiplexing part and non-multiplexed part of the same operating cycle, in order to reduce computational latency and improve the decoding efficiency; the wrong place and wrong value of the solution to the use of look-up table Completion of the Forney algorithm coefficient multiplication, and the inverse lookup table multiplexing and the same coefficient of Qian search search sub-unit, in order to reduce resource consumption by the rate-selective signal, you can choose RS (255,223) and RS (255,239) 2 kinds of decoding modes.The hardware implementation of this multi-rate decoder is realized by FPGA (Field Pro-grammable Gate Array) of Altera Company, the result shows that this decoder consumes 2981 logic units and 9472 bit Of the memory resources, much lower than the sum of the two single code rate decoder consume resources.