在静态存储器(SRAM)抗辐射加固设计中,单错误纠错码(SEC)联合交织是解决空间SRAM多比特翻转(MBU)的有效方法。交织距离(ID)的选择应当使MBU分布在不同的物理字中,ID越大,电路实现越复杂,功耗和面积也越大。基于SRAM在空间产生的MBU错误图样以及数目,在已有的ID选择模型上进行修正,提出了一种精确的评估模型。 In static memory (SRAM) radiation resistant design, single error error correction code (SEC) joint interleaving is an effective way to solve spatial SRAM multi-bit inversion (MBU). The interleaving distance (ID) should be chosen such that the MBUs are distributed among different physical words. The larger the ID, the more complex the circuit is and the larger the power consumption and the area are. Based on the MBU error pattern and the number of space-generated SRAM in the SRAM, the existing ID selection model is modified to provide an accurate evaluation model.