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本文提出一种算法,用于半导体随机线选法存储系统中检测和诊断地址寄存器、译码器和数码寄存器等各种固定性故障。应用一个外加测试器,它只通过公共的控制信号、电源线、地址寄存器和数码寄存器与存储系统联系,也就是说测试系统不可能访问存储系统其他部分时可应用此算法。当测试系统的部件(地址寄存器,译码器等)时,不需要假定未经测试的部件无故障。详细地讨论了因故障屏蔽所引起的问题。同时这个分析也允许有故障时同时存取二个或更多的字的情况。要区分故障和失效两个不同的概念,逻辑门和位线等处于死1或死0状态称为故障,因固定逻辑故障引起存储器不能正常工作称为失效,地址寄存器测试算法串行逐位地对地址寄存器的每一位进行测试,而对一个 n 位的地址寄存器进行完全测试要求取数约7n 至10n 次。算法要求至少存在一个功能存储位线和一个地址寄存器位的组合,并且当出现多重故障时该算法仍有效。虽然与某一地址寄存器位相连接的译码器和存储元件的故障综合,恰好与这一地址位的故障现象相同,因而可能屏蔽这一无故障的地址位,但仍有可能正确诊断地址位的故障。译码器测试算法检验2~n 根译码输出线,且能决定是否含有一根失效线。整个译码器的测试要求取数次数约(n+2)2~n 次,并基于“非创造”(noncreative)网络的概念,限制译码输出线的失效类型。测试过地址寄存器和译码器之后,证明其不存在故障,郡么再采用普通的读/写技术测试数码寄存器和存储器阵列。
This paper presents an algorithm for detecting and diagnosing various fixed faults, such as address registers, decoders and digital registers, in semiconductor random line select storage systems. An additional tester is used which communicates with the storage system only through common control signals, power lines, address registers and digital registers, which means that the test system can apply this algorithm when it is not possible to access other parts of the storage system. When testing the system’s components (address registers, decoders, etc.), it is not necessary to assume that the untested part is not fault-free. Discussed in detail the problems caused by fault shielding. This analysis also allows two or more words to be accessed simultaneously in the event of a failure. To distinguish between the two different concepts of failure and failure, the logic gates and bit lines are dead 1 or dead 0 states called faults due to fixed logic faults that cause the memory to not work properly, called the address register test algorithm serial bit by bit Each bit in the address register is tested, and an n-bit address register for a complete test requires a count of about 7n to 10n times. The algorithm requires at least one combination of a functional memory bit line and an address register bit, and the algorithm is still valid in the case of multiple faults. Although the fault synthesis of the decoder and memory elements connected to a certain address register bit happens to be identical to the fault of this address bit, it is possible to mask this fault-free address bit but it is still possible to correctly diagnose the address bit malfunction. Decoder test algorithm test 2 ~ n decoding output line, and can determine whether to include a failure line. The test requirements of the decoder as a whole are about (n + 2) 2 ~ n times, and based on the concept of “noncreative” network, the type of failure of the decoding output line is limited. After testing the address register and decoder, to prove that there is no fault, the county then use ordinary read / write technology to test digital registers and memory arrays.